1. Field of the Invention
The invention relates generally to a nonvolatile semiconductor memory device. More particularly, the invention relates to a nonvolatile semiconductor memory device constructed with bitlines extending from a cell array in a single direction.
A claim of priority is made to Korean Patent Application No. 2005-81553, filed on Sep. 2, 2005, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
A conventional nonvolatile semiconductor memory device comprises a plurality of memory cells arranged in a cell array, and various peripheral circuits adapted to control the transfer of data to and from the cell array. The memory cells in the cell array are connected to a plurality of corresponding bitlines used to transfer data to and from the memory cells. Each of the bitlines can be individually controlled by either charging it to a power source voltage or discharging it to ground using a voltage control block.
FIGS. 1 and 2 are circuit and layout diagrams showing interconnections between bitlines and voltage control blocks in a conventional nonvolatile semiconductor memory device.
Referring to FIGS. 1 and 2, the conventional nonvolatile semiconductor memory device comprises a cell array 10, a lower voltage control block 20, and an upper voltage control block 30.
Cell array 10 contains a plurality of bitlines extending up and down. In particular, cell array 10 comprises four bitlines BL1, BL2, BL5, and BL6 extending down into lower voltage control block 20, and four bitlines BL3, BL4, BL7, and BL8 extending up into upper voltage control block 30. Bitlines BL1 through BL8 are formed in respective bit layers BMT connected to voltage control blocks 20 and 30. In the conventional nonvolatile semiconductor memory device shown in FIGS. 1 and 2, pairs of adjacent bitlines extending in the same direction are coupled to respective latch blocks 41, 42, 43, or 44.
FIGS. 3 and 4 show respective layout patterns for voltage control blocks 20 and 30. In FIGS. 3 and 4, power source voltage lines 21, 25, 31, and 35 are connected to a power source supplying a power source voltage VDD, and ground voltage lines 23, 27, 33, and 37 are connected to ground. Power source voltage lines 21, 25, 31, and 35, and ground voltage lines 23, 27, 33, and 37 are formed in a metal layer MET, which is formed after bit layers BMT.
Power source voltage lines, 21, 25, 31, and 35, and ground voltage lines, 23, 27, 33, and 37, are connected to source/drain junctions of respective pre-charging and discharging transistors TD and TS through respective bit layers (BMT) 26 and 28 (See, FIGS. 1 and 5). Thus, when bitlines BL1 through BL8 extend toward a single side of cell array 10, half of bitlines BL1 through BL8 intersect bit layers, 26 and 28, which are respectively connected to power source voltage VDD and ground VSS. Accordingly, bitlines BL1 through BL8 are generally divided in half between lower and upper voltage control blocks 20 and 30.
In the conventional nonvolatile semiconductor memory device employing lower and upper control blocks 20 and 30, the timing of data passing through lower and upper control blocks 20 and 30 can be skewed due to slight differences in the lengths of data buses carrying the data. The data skew tends to complicate the design of control circuits used to operate the semiconductor memory device.
Furthermore, by having bitlines extending in more than one direction away from the cell array, the size of the memory device is significantly increased.